Design and demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 115-121).Complementary-Metal-Oxide-Semiconductor (CMOS) feature size scaling has resulted in significant improvements in the performance and energy efficiency of integrated circuits in the past 4 decades. However, in the last decade and for technology nodes below 90 nm, the scaling of threshold and supply voltages has slowed, as a result of subthreshold leakage, and power density has increased with each new technology node. This has forced a move toward multi-core architectures, but the energy efficiency benefits of parallelism are limited by the sub-thresahold leakage and the minimum energy point for a given function. Avoiding this roadblock requires an alternative device with more ideal switching characteristics. One promising class of such devices is the electro-statically actuated micro-electro-mechanical (MEM) relay which offers zero leakage current and abrupt turn-on behavior. Although a MEM relay is inherently slower than a CMOS transistor due to the mechanical movement, we have developed circuit design methodologies to mitigate this problem at the system level. This thesis explores such design optimization techniques and investigates the viability of MEM relays as an alternative switching technology for very-large scale integration (VLSI) applications. In the first part of this thesis, the feasibility of MEM relays for power management applications is discussed. Due to their negligibly low leakage, in certain applications, chips utilizing power gates built with MEM relays can achieve lower total energy than those built with CMOS transistors. A simple comparative analysis is presented and provides design guidelines and energy savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. We also demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based pulse generator suitable for self-timed operation. Going beyond power-gating applications, this work also describes circuit techniques and trade-offs for logic design with MEM-relays, focusing on multipliers which are commonly known as the most complex arithmetic units in a digital system. These techniques leverage the large disparity between mechanical and electrical time-constants of a relay, partitioning the logic into large, complex gates to minimize the effect of mechanical delay and improve circuit performance. At the component design level, innovations in compressor unit design minimize the required number of relays for each block and facilitate component cascading with no delay penalty. We analyze the area/energy/delay trade-offs vs. CMOS designs, for typical bit-widths, and show that scaled relays offer 10-20x lower energy per operation for moderate throughputs (<10-100MOPS). In addition to this analysis, we demonstrate the functionality of some of the most complex MEM relay circuits reported to date. Finally, considering the importance of signal generation and transmission in VLSI systems, this thesis presents MEM relay-based I/O units, focusing on design and demonstration of digital to analog converters (DAC). It also explores the concept of faster-than-mechanical-delay signal transmission.by Hossein Fariborzi.Ph.D

Multilayer Ferromagnetic Spintronic Devices for Neuromorphic Computing Applications

Spintronics has gone through substantial progress due to its applications in energy-efficient memory, logic and unconventional computing paradigms. Multilayer ferromagnetic thin films are extensively studied for understanding the domain wall and skyrmion dynamics. However, most of these studies are confined to the materials and domain wall/skyrmion physics. In this paper, we present the experimental and micromagnetic realization of a multilayer ferromagnetic spintronic device for neuromorphic computing applications. The device exhibits multilevel resistance states and the number of resistance states increases with lowering temperature. This is supported by the multilevel magnetization behavior observed in the micromagnetic simulations. Furthermore, the evolution of resistance states with spin-orbit torque is also explored in experiments and simulations. Using the multi-level resistance states of the device, we propose its applications as a synaptic device in hardware neural networks and study the linearity performance of the synaptic devices. The neural network based on these devices is trained and tested on the MNIST dataset using a supervised learning algorithm. The devices at the chip level achieve 90\% accuracy. Thus, proving its applications in neuromorphic computing. Furthermore, we lastly discuss the possible application of the device in cryogenic memory electronics for quantum computers

Theoretical Study of Field-Free Switching in PMA-MTJ Using Combined Injection of STT and SOT Currents

Field-free switching in perpendicular magnetic tunnel junctions (P-MTJs) can be achieved by combined injection of spin-transfer torque (STT) and spin-orbit torque (SOT) currents. In this paper, we derived the relationship between the STT and SOT critical current densities under combined injection. We included the damping–like torque (DLT) and field-like torque (FLT) components of both the STT and SOT. The results were derived when the ratio of the FLT to the DLT component of the SOT was positive. We observed that the relationship between the critical SOT and STT current densities depended on the damping constant and the magnitude of the FLT component of the STT and the SOT current. We also noted that, unlike the FLT component of SOT, the magnitude and sign of the FLT component of STT did not have a significant effect on the STT and SOT current densities required for switching. The derived results agreed well with micromagnetic simulations. The results of this work can serve as a guideline to model and develop spintronic devices using a combined injection of STT and SOT currents

EAMTR: Energy aware multi-tree routing for wireless sensor networks

IEEE 802.15.4 is the prevailing standard for low-rate wireless personal area networks. It specifies the physical layer and medium access control sub-layer. Some emerging standards such as ZigBee define the network layer on top of these lower levels to support routing and multi-hop communication. Tree routing is a favourable basis for ZigBee routing because of its simplicity and limited use of resources. However, in data collection systems that are based on spanning trees rooted at a sink node, non-optimal route selection, congestion and uneven distribution of traffic in tree routing can adversely contribute to network performance and lifetime. The imbalance in workload can result in hotspot problems and early energy depletion of specific nodes that are normally the crucial routers of the network. The authors propose a novel light-weight routing protocol, energy aware multi-tree routing (EAMTR) protocol, to balance the workload of data gathering and alleviate the hotspot and single points of failure problems for high-density sink-type networks. In this scheme, multiple trees are formed in the initialisation phase and according to network traffic, each node selects the least congested route to the root node. The results of simulation and performance evaluation of EAMTR show significant improvement in network lifetime and traffic distribution

A numerical analysis and experimental demonstration of a low degradation conductive bridge resistive memory device

This study investigates a low degradation metal-ion conductive bridge RAM (CBRAM) structure. The structure is based on placing a diffusion blocking layer (DBL) between the device's top electrode (TE) and the resistive switching layer (RSL), unlike conventional CBRAMs, where the TE serves as a supply reservoir for metallic species diffusing into the RSL to form a conductive filament (CF) and is kept in direct contact with the RSL. The properties of a conventional CBRAM structure (Cu/HfO2/TiN), having a Cu TE, 10 nm HfO2 RSL, and a TiN bottom electrode, are compared with a 2 nm TaN DBL incorporating structure (Cu/TaN/HfO2/TiN) for 103 programming and erase simulation cycles. The low and high resistive state values for each cycle are calculated and the analysis reveals that adding the DBL yields lower degradation. In addition, the 2D distribution plots of oxygen vacancies, O ions, and Cu species within the RSL indicate that oxidation occurring in the DBL-RSL interface results in the formation of a sub-stoichiometric tantalum oxynitride with higher blocking capabilities that suppresses further Cu insertion beyond an initial CF formation phase, as well as CF lateral widening during cycling. The higher endurance of the structure with DBL may thus be attributed to the relatively low amount of Cu migrating into the RSL during the initial CF formation. Furthermore, this isomorphic CF displays similar cycling behavior to neural ionic channels. The results of numerical analysis show a good match to experimental measurements of similar device structures as well.Published versio

A parity checker circuit based on microelectromechanical resonator logic elements

Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro-resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized. (C) 2017 Elsevier B.V. All rights reserved

Bitwise Logical Operations in VCMA-MRAM

Today&rsquo;s technology demands compact, portable, fast, and energy-efficient devices. One approach to making energy-efficient devices is an in-memory computation that addresses the memory bottleneck issues of the present computing system by utilizing a spintronic device viz. magnetic tunnel junction (MTJ). Further, area and energy can be reduced through approximate computation. We present a circuit design based on the logic-in-memory computing paradigm on voltage-controlled magnetic anisotropy magnetoresistive random access memory (VCMA-MRAM). During the computation, multiple bit cells within the memory array are selected that are in parallel by activating multiple word lines. The designed circuit performs all logic operations-Read/NOT, AND/NAND, OR/NOR, and arithmetic SUM operation (1-bit approximate adder with 75% accuracy for SUM and accurate carry out) by slight modification using control signals. All the simulations have been performed at a 45 nm CMOS technology node with VCMA-MTJ compact model by using the HSPICE simulator. Simulation results show that the proposed circuit&rsquo;s approximate adder consumes about 300% less energy and 2.3 times faster than its counterpart exact adder

Microelectromechanical resonator based digital logic elements

Micro/nano-electromechanical resonator based mechanical computing has recently attracted significant attention. However, its full realization has been hindered by the difficulty in realizing complex combinational logics, in which the logic function is constructed by cascading multiple smaller logic blocks. In this work we report an alternative approach for implementation of digital logic core elements, multiplexer and demultiplexer, which can be used to realize combinational logic circuits by suitable concatenation. Toward this, shallow arch shaped microresonators are electrically connected and their resonance frequencies are tuned based on an electrothermal frequency modulation scheme. This study demonstrates that by reconfiguring the same basic building block, the arch microresonator, complex logic circuits can be realized

Bitwise Logical Operations in VCMA-MRAM

Today’s technology demands compact, portable, fast, and energy-efficient devices. One approach to making energy-efficient devices is an in-memory computation that addresses the memory bottleneck issues of the present computing system by utilizing a spintronic device viz. magnetic tunnel junction (MTJ). Further, area and energy can be reduced through approximate computation. We present a circuit design based on the logic-in-memory computing paradigm on voltage-controlled magnetic anisotropy magnetoresistive random access memory (VCMA-MRAM). During the computation, multiple bit cells within the memory array are selected that are in parallel by activating multiple word lines. The designed circuit performs all logic operations-Read/NOT, AND/NAND, OR/NOR, and arithmetic SUM operation (1-bit approximate adder with 75% accuracy for SUM and accurate carry out) by slight modification using control signals. All the simulations have been performed at a 45 nm CMOS technology node with VCMA-MTJ compact model by using the HSPICE simulator. Simulation results show that the proposed circuit’s approximate adder consumes about 300% less energy and 2.3 times faster than its counterpart exact adder

Axially modulated arch resonator for logic and memory applications

We demonstrate reconfigurable logic and random access memory devices based on an axially modulated clamped-guided arch resonator. The device is electrostatically actuated and the motional signal is capacitively sensed, while the resonance frequency is modulated through an axial electrostatic force from the guided side of the microbeam. A multi-physics finite element model is used to verify the effectiveness of the axial modulation. We present two case studies: first, a reconfigurable two-input logic gate based on the linear resonance frequency modulation, and second, a memory element based on the hysteretic frequency response of the resonator working in the nonlinear regime. The energy consumptions of the device for both logic and memory operations are in the range of picojoules, promising for energy efficient alternative computing paradigm